Page 113 - Hardware Implementation of Finite-Field Arithmetic

96 Cha pte r F o u r

A complete VHDL file nr_divider.vhd is available at www.
arithmetic-circuits.org. The entity declaration is

entity nr_divider is
port (
a, b: in std_logic_vector (K-1 downto 0);
clk, reset, start: in std_logic;
quotient, remainder: out std_logic_vector (K-1 downto 0);
done: out std_logic
);
end nr_divider;

The VHDL architecture corresponding to the circuit of Fig. 4.1 is
the following:

parallel_register: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then s <= zero & a;
elsif update = ‘1’ then
s(2*K-1 downto 1) <= r(2*K-2 downto 0);
s(0) <= ‘0’;
end if;
end if;
end process parallel_register;
shift_register: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then q <= short_zero;
elsif update = ‘1’ then
for i in K-1 downto 2 loop q(i) <= q(i-1); end loop;
q(1) <= not(s(2*K-1));
end if;
end if;
end process shift_register;
with s(2*K-1) select r(2*K-2 downto k-2) <=
s(2*K-2 downto k-2) + b when ‘1’,
s(2*K-2 downto K-2) - b when others;
r(K-3 downto 0) <= s(K-3 downto 0);
modified_q <= not(q(K-1))&q(K-2 downto 1)&’1’;
with s(2*K-1) select quotient <=
modified_q when ‘0’, modified_q -1 when others;
with s(2*K-1) select remainder <=
s(2*K-2 downto K-1) when ‘0’, s(2*K-2 downto K-1) + b
when others;
The complete model additionally includes a (k − 1)-state counter
and a control unit.

4.1.2 Multiplication and Subtraction
It has been observed [DBS06] that in system [Eq. (4.8)] u(i) belongs to
the interval − px/2 ≤ u(i) < px/2, for all i in 0, 1, . . . , n − 1. As both p and