Page 154 - Hardware Implementation of Finite-Field Arithmetic

Operations over Z [ x ]/ f ( x ) 137
p

p m LUTs Slices Total time
17 8 40 24 8
239 17 136 68 10

TABLE 5.2 Cost and Delay of Subtractors of
Polynomials mod p

5.5.3 Adders/Subtractors of Polynomials mod p
The cost and delay of several subractors are shown in Table 5.3.

p m LUTs Slices Total time
17 8 112 64 10
239 17 425 221 12

TABLE 5.3 Cost and Delay of Adders/Subtractors of
Polynomials mod p

5.5.4 Serial Multipliers
17
17
The circuits are for 239 with irreducible polynomial f(x) = x + 237.
The parameter Mult 18 × 18 represents the number of embedded
multipliers used in the Xilinx FPGAs. The cost and delay of these
serial multipliers are shown in Table 5.4.

Mult
p m FFs LUTs Slices 18 × 18 Period Cycles Total time
MSE-first 239 17 303 1,690 937 17 26.1 34 888
LSE-first 239 17 415 1,779 1,061 18 19.4 17 330

TABLE 5.4 Cost and Delay of Serial Multipliers

5.5.5 Exponentiation
17
17
The circuit is for 239 with irreducible polynomial f(x) = x + 237. The
parameter Mult 18 × 18 represents the number of embedded
multipliers used in the Xilinx FPGAs.

Mult Total
p m FFs LUTs Slices 18 × 18 Period Cycles time
239 17 1,241 3,989 2,318 36 19.5 289 5636