Page 206 - Hardware Implementation of Finite-Field Arithmetic

186 Cha pte r Se v e n

data_path: montg_cell port map (C=>cc,B=>bb,a_i=>aa(0),new_
c=>new_c);
counter: process(reset, clk)
begin
if reset = ‘1’ then count <= 0;
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then
count <= 0;
elsif shift_r = ‘1’ then
count <= count+1;
end if;
end if;
end process counter;
sh_register_A: process(clk)
begin
if reset = ‘1’ then
aa <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then
aa <= a;
else
aa <= ‘0’ & aa(M-1 downto 1);
end if;
end if;
end process sh_register_A;
register_B: process(clk)
begin
if reset = ‘1’ then
bb <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then
bb <= b;
end if;
end if;
end process register_B;
register_C: process(inic, clk)
begin
if inic = ‘1’ or reset = ‘1’ then
cc <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if ce_c = ‘1’ then
cc <= new_c;
end if;
end if;
end process register_C;
z <= cc;
control_unit: process(clk, reset, current_state)
begin
case current_state is
when 0 to 1 => inic<=’0’; shift_r<=’0’; done<=’1’;
ce_c<=’0’;
when 2 => inic <= ‘1’; shift_r <= ‘0’; done <= ‘0’;
ce_c <= ‘0’;
when 3 => inic <= ‘0’; shift_r <= ‘1’; done <= ‘0’;
ce_c <= ‘1’;