Page 226 - Hardware Implementation of Finite-Field Arithmetic

206 Cha pte r Se v e n

entity binary_algorithm_polynomials is
port(
g, h: in std_logic_vector(m-1 downto 0);
clk, reset, start: in std_logic;
z: out std_logic_vector(m-1 downto 0);
done: out std_logic
);
end binary_algorithm_polynomials;
The VHDL architecture corresponding to the circuit of Fig. 7.8
follows:

first_iteration: for i in 0 to m-2 generate
next_b(i) <=
(b(0) and (b(i+1) xor a(i+1))) or (not(b(0)) and
b(i+1));
end generate;
next_b(m-1) <= b(0) and a(m);
next_d(m-1) <= (b(0) and (d(0) xor c(0))) or (not(b(0))
and d(0));
second_iteration: for i in 0 to m-2 generate
next_d(i) <=
(f(i+1) and next_d(m-1)) xor ((b(0) and (d(i+1) xor
c(i+1))) or (not(b(0)) and d(i+1)));
end generate;
registers_ac: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then a <= f; c <= (others => ‘0’);
elsif ce_ac = ‘1’ then a <= ‘0’&b; c <= d;
end if;
end if;
end process registers_ac;
registers_bd: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then b <= h; d <= g;
elsif ce_bd = ‘1’ then b <= next_b; d <= next_d;
end if;
end if;
end process registers_bd;
Additionally, the circuit includes components for storing and
updating the variables alpha and beta as well as a control unit.
It is important to note that the algorithms used for division can
also be used for inversion.

7.5 Inversion
The multiplicative inverse a − 1 (x) of a(x) in the finite field GF(2 ) is
m
− 1
defined as the element that satisfies a(x)⋅a (x) = 1, where “⋅” denotes
multiplication in GF(2 ). The most popular methods for finite field
m