Page 229 - Hardware Implementation of Finite-Field Arithmetic

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Operations over GF (2 )—Polynomial Bases 209

A generic VHDL model EEA_inversion.vhd has been generated.
The complete VHDL file is available at www.arithmetic-circuits.org.
The entity declaration is

entity eea_inversion is
port (
A: in std_logic_vector (M-1 downto 0);
clk, reset, start: in std_logic;
Z: out std_logic_vector (M-1 downto 0);
done: out std_logic
);
end eea_inversion;
The VHDL architecture corresponding to the EEA_inversion
follows:

Comb: process(r,s,u,v,d)
begin
if R(m) = ‘0’ then
new_R <= R(M-1 downto 0) & ‘0’;
new_U <= U(M-1 downto 0) & ‘0’;
new_S <= S;
new_V <= V;
new_d <= d + 1;
else
if d = ZERO then
if S(m) = ‘1’ then
new_R <= (S(M-1 downto 0) xor R(M-1 downto 0))
& ‘0’;
new_U <= (V(M-1 downto 0) xor U(M-1 downto 0))
& ‘0’;
else
new_R <= S(M-1 downto 0) & ‘0’;
new_U <= V(M-1 downto 0) & ‘0’;
end if;
new_S <= R;
new_V <= U;
new_d <= (0=> ‘1’, others => ‘0’);
else --d /= ZERO
new_R <= R;
new_U <= ‘0’ & U(M downto 1);
if S(m) = ‘1’ then
new_S <= (S(M-1 downto 0) xor R(M-1 downto 0))
& ‘0’;
new_V <= (V xor U);
else
new_S <= S(M-1 downto 0) & ‘0’;
new_V <= V;
end if;
new_d <= d - 1;
end if;
end if;
end process;