Page 222 - Hardware Implementation of Finite-Field Arithmetic

202 Cha pte r Se v e n

The corresponding VHDL architecture follows:
RR <= R_BY_R; -- precomputed constant (R*R mod F), R = 2^K
inst_mult: montgomery_mult port map (A => cc, B => bb,
clk => clk, reset => reset, start => strt_mul, Z => new_B,
done => done_mult);
inst_square: montgomery_squarer port map (A => cc, clk =>
clk, reset => reset, start => strt_sq, Z => new_c, done
=> done_sq);
counter: process(reset, clk)
begin
if reset = ‘1’ then count <= 0;
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then count <= 0;
elsif shift_r = ‘1’ then count <= count+1; end if;
end if;
end process counter;
sh_reg_e: process(reset, clk)
begin
if reset = ‘1’ then ee <= (others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then ee <= e;
elsif shift_r = ‘1’ then ee <= ‘0’ & ee(N-1 downto 1);
end if;
end if;
end process sh_reg_e;
register_c: process(reset, clk)
begin
if reset = ‘1’ then cc <= (others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if first = ‘1’ then cc <= r_by_r;
elsif inic = ‘1’ then cc <= new_b;
elsif shift_r = ‘1’ then cc <= new_c;
elsif last = ‘1’ then cc <= (0 => ‘1’, others => ‘0’);
end if;
end if;
end process register_c;
register_b: process(reset, clk)
begin
if reset = ‘1’ then bb <= (others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if first = ‘1’ then bb <= a;
elsif inic = ‘1’ then bb <= F;
elsif (shift_r = ‘1’ and ee(0) = ‘1’) or (capt = ‘1’)
then bb <= new_b; end if;
end if;
end process register_b;
b <= bb;
control_unit: process(clk, reset, current_state, ee(0))
begin
case current_state is
when 0 to 1 => inic <=’0’; shift_r <=’0’; done <=’1’;
first <=’0’; strt_sq <= ‘0’; strt_mul <= ‘0’; last
<= ‘0’; capt <= ‘0’;