Page 218 - Hardware Implementation of Finite-Field Arithmetic

198 Cha pte r Se v e n

end process counter_sq;
counter: process(reset, clk)
begin
if reset = ‘1’ then count <= 0;
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then count <= 0;
elsif shift_r = ‘1’ then count <= count+1; end if;
end if;
end process counter;
sh_reg_e: process(reset, clk)
begin
if reset = ‘1’ then ee <= (others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then ee <= e;
elsif shift_r = ‘1’ then ee <= ‘0’ & ee(N-1 downto 1);
end if;
end if;
end process sh_reg_e;
register_c: process(reset, clk)
begin
if reset = ‘1’ then cc <= (others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then cc <= a;
elsif shift_r = ‘1’ then cc <= new_c; end if;
end if;
end process register_c;
register_b: process(reset, clk)
begin
if reset = ‘1’ then bb <= (0 => ‘1’, others => ‘0’);
elsif clk’ event and clk = ‘1’ then
if inic = ‘1’ then bb <= (0 => ‘1’, others => ‘0’);
elsif shift_r = ‘1’ and ee(0) = ‘1’ then bb <= new_b;
end if;
end if;
end process register_b;
control_unit: process(clk, reset, current_state, ee(0))
begin
case current_state is
when 0 to 1 => inic <= ‘0’; shift_r <=’0’; done <=’1’;
ce_c <=’0’; start_sq <= ‘0’; start_mult <= ‘0’;
when 2 => inic <= ‘1’; shift_r <= ‘0’; done <= ‘0’;
ce_c <= ‘0’; start_sq <= ‘0’; start_mult <= ‘0’;
when 3 => inic <= ‘0’; shift_r <= ‘0’; done <= ‘0’;
ce_c <= ‘1’; start_sq <= ‘1’; start_mult <= ee(0);
when 4 => inic <= ‘0’; shift_r <= ‘0’; done <= ‘0’;
ce_c <= ‘1’; start_sq <= ‘0’; start_mult <= ‘0’;
when 5 => inic <= ‘0’; shift_r <= ‘1’; done <= ‘0’;
ce_c <= ‘1’; start_sq <= ‘0’; start_mult <= ‘0’;
end case;
if reset = ‘1’ then current_state <= 0;
elsif clk’event and clk = ‘1’ then
case current_state is
when 0 => if start = ‘0’ then current_state <= 1;
end if;