Page 214 - Hardware Implementation of Finite-Field Arithmetic

194 Cha pte r Se v e n

An executable Ada file LSBfirst_squarer_v2.adb, including Algo-
rithm 7.15, is available at www.arithmetic-circuits.org.
A VHDL model for the LSB-first squaring algorithm (version 2,
Algorithm 7.15) is given in the file LSB_first_squarer_V2.vhd, which
is available at www.arithmetic-circuits.org. This model includes the
component LSB_first_squarer_cell, with the following architecture:

new_b_calc: for i in 2 to M-1 generate
new_b(i) <= B(i-2) xor (B(m-1) and Faux(i)) xor (B(m-2)
and F(i));
end generate;
new_b(1) <= (B(m-1) and Faux(1)) xor (B(m-2) and F(1));
new_b(0) <= (B(m-1) and Faux(0)) xor (B(m-2) and F(0));
new_w_calc: for i in 0 to M-1 generate
new_w(i) <= w(i) xor (b(i) and a_k);
end generate;

The entity declaration of the LSB-first squaring circuit given in
the VHDL file LSB_first_squarer_V2.vhd is

entity LSB_first_squarer is
port (
A: in std_logic_vector (M-1 downto 0);
clk, reset, start: in std_logic;
Z: out std_logic_vector (M-1 downto 0);
done: out std_logic
);
end LSB_first_squarer;
The corresponding VHDL architecture follows:

basicCell: LSB_first_squarer_cell port map (
b => b, w => w, a_k => aa(0), new_b => new_b, new_w =>
new_w );
register_A: process(reset, clk)
begin
if reset = ‘1’ then aa <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then aa <= a(M-1 downto (M+1)/2);
else aa <= ‘0’ & aa(M/2-1 downto 1); end if;
end if;
end process register_A;
register_b: process(reset, clk)
begin
if reset = ‘1’ then b <= (others => ‘0’);
elsif clk’event and clk = ‘1’ then
if inic = ‘1’ then
if M mod 2 = 0 then b <= F;
else b <= product_alphaF; end if;
elsif ce_c = ‘1’ then b <= new_b; end if;
end if;
end process register_b;