Page 348 - Hardware Implementation of Finite-Field Arithmetic

328 App endix B

five times the computation time of a mod f(x) multiplier. A VHDL model
has been generated. The complete VHDL file mod_f_divider.vhd is
available at www.arithmetic-circuits.org. The entity declaration is
entity mod_f_divider is
port(
g, h: in polynomial;
clk, reset, start: in std_logic;
z: out polynomial;
done: out std_logic
);
end mod_f_divider;
The VHDL architecture corresponding to the circuit of Fig. B.1 is
the following:
with j select aj <=
a(0) when “000”, a(1) when “001”, a(2) when “010”,
a(3) when “011”, a(4) when “100”, a(5) when others;
with j select fji <=
f12(0) when “000”, f12(1) when “001”, f12(2) when
“010”, f12(3) when “011”, f12(4) when “100”, f12(5) when
others;
fji_selection: for i in 1 to 5 generate
with sel_f select f12(i) <= f1(i) when ‘0’, f2(i) when
others;
end generate;
f12(0) <= x”00000001”;
with sel_e select in2 <= fji when ‘0’, inv when others;
with sel_ahg select ahg <= a when “00”, h when “01”,
g when others;
with sel_a select next_a <= e when ‘1’, product_f when
others;
first_component: dar_csa_multiplier port map(
x => aj, y => in2, clk => clk, reset => reset,
start => start_mult_p, z => product_p,
done => mult_p_done
);
second_component: mod_f_multiplier port map(
a => e, b => ahg, clk => clk, reset => reset,
start => start_mult_f, z => product_f,
done => mult_f_done
);
third_component: plus_minus port map(
x => x”00000001”, y => a(0), clk => clk, reset => reset,
start => start_inv, z => next_inv, done => inv_done
);
register_a: process(clk)
begin
if clk’event and clk = ‘1’ then
if load = ‘1’ then a <= h;
elsif ce_a = ‘1’ then a <= next_a;