Page 351 - Hardware Implementation of Finite-Field Arithmetic

APPENDIX C

Binary Fields

163
C.1 GF(2 )
163
GF(2 ) is represented by the set of polynomials of degree smaller
7
163
than 163 over GF(2), modulo the irreducible polynomial f(x) = x + x +
3
x + x + 1.
6
C.1.1 mod f(x) Multiplication
Several combinational (classic_multiplication,mastrovito_V2_multiplication)
and sequential (interleaved_mult, montgomery_mult) entities have been
described in Chap. 7. The parameter values are the following:
constant M: integer := 163;
constant F: std_logic_vector(M-1 downto 0):=
“000”&x”00000000000000000000000000000000000000C9”;
In the case of the interleaved multiplier, several implementation
strategies, based on the number G of bits computed at each cycle,
have been considered. The implementation results (Spartan3, speed-5)
are given in Table C.1.
All the source files are available at www.arithmetic-circuits.org.

C.1.2 mod f(x) Division
Generic VHDL models of mod f(x) dividers (binary_algorithm_
163
polynomials.vhd) have been defined in Sec. 7.4. In the case of GF(2 )
the parameter values are the following:
constant M: integer := 163;
--logM is the number of bits of M plus an additional sign
--bit:
constant logM: integer := 9;
constant F: std_logic_vector(M downto 0) :=
x”800000000000000000000000000000000000000C9”;

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