Page 354 - Hardware Implementation of Finite-Field Arithmetic

334 App endix C

C.2.2 mod f(x) Division
Generic VHDL models of mod f(x) dividers (binary_algorithm_
233
polynomials.vhd) have been defined in Sec. 7.4. In the case of GF(2 )
the parameter values are the following:
constant M: integer := 233;
--logM is the number of bits of M plus an additional sign
--bit:
constant logM: integer := 9;
constant F: std_logic_vector(M downto 0) :=
(0=> ‘1’, 74 => ‘1’, 233 => ‘1’,others => ‘0’);

The implementation results (Spartan3, speed-5) are the following:
FFs LUTs Slices Period AverCycles AverTime
962 1,013 763 7.4 466 3448

The source file is available at www.arithmetic-circuits.org.
C.2.3 Squaring
According to the results of Chap. 7 the best solution is a combinational
circuit modeled by the classic_squarer entity. The parameter values are
the same as before (Sec. 2.1), and the implementation results (Spartan3,
speed-5) are the following:

LUTs Slices Total time
153 99 3

The source file is available at www.arithmetic-circuits.org.

C.2.4 Elliptic-Curve Operations
Circuits for executing the elliptic-curve operations over K-233 have
also been generated, namely K233_addition.vhd and K233_ point_
multiplication.vhd. They are available at www.arithmetic-circuits.org.
The parameter definition packages and the entity declarations are
package K233_addition_parameters is
constant m: natural := 233;
constant logm: natural := 8;
end K233_addition_parameters;

entity K233_addition is
port(
x1, y1, x2, y2: in std_logic_vector(m-1 downto 0);
clk, reset, start: in std_logic;
x3: inout std_logic_vector(m-1 downto 0);
y3: out std_logic_vector(m-1 downto 0);
done: out std_logic
);