Page 359 - Hardware Implementation of Finite-Field Arithmetic

Ada versus VHDL 339

if quotient(s,y) = 1 then r := s - y;
elsif quotient(s,y) = 0 then r := s;
else r := s + y;
end if;
s := 2*r;
end loop;
z := r / (2**(n-k));
if z < 0 then z := (z + m); end if;
end nr_reducer;
The differences between Algorithm D.1 and D.2 are the following:
In VHDL z must be declared as inout because the value of the
output variable z is used internally (if z < 0 then z := (z +
m); end if;); in Ada z is an output parameter;
In VHDL y, s, and r are variables (neither signals nor constants)
and must be explicitly declared as variables; in Ada there are no
signals and the constant declaration is slightly different; see an
example below:

n: constant integer := 20; --(Ada)
constant n: integer := 20; --(VHDL)

In VHDL the index ranges are defined with to or downto; in Ada
with .. ; for example,

for i in 0 to n-k -- (VHDL)
for i in 0 .. n-k -- (Ada)

or

for i in n-k downto 0 -- (VHDL)
for i in reverse 0 .. n-k -- (Ada)
Regarding the way the source files are generated, there is another
difference between Ada and VHDL. In VHDL all the source units
(entities, architectures, packages, package bodies) can be stored
within the same file, or within separate files. In Ada, every unit is
stored within a separate file: an .ads file storing the external view of
the corresponding unit, and an .adb file storing the corresponding
internal definition.
In order to execute the Ada procedure (Algorithm D.2) with actual
values of m and x, the value of the constants n and k are defined
within reducer_parameters.ads

package reducer_parameters is
n: constant natural := 20;
k: constant natural := 8;
end reducer_parameters;