Page 358 - Hardware Implementation of Finite-Field Arithmetic

338 App endix D

else r := s + y;
end if;
s := 2*r;
end loop;
z := r / (2**(n-k));
if z < 0 then z := (z + m); end if;
end nr_reducer;

In order to execute this procedure with actual values of m and x,
the following test_reducer entity could be defined and simulated:

--define the value of n and k:
package test_reducer_parameters is
constant n: integer := 20;
constant k: integer := 8;
end test_reducer_parameters;
use work.test_reducer_parameters.all;
entity test_reducer is end test_reducer;

architecture Ada_style of test_reducer is
--insert here Algorithm 1
signal m, x, z: integer;
begin
m <= 239;
x <= 123456, 654321 after 100 ns, 555555 after 200 ns;
process(m, x)
variable var_z: integer;
begin
nr_reducer(m, x, var_z);
z <= var_z;
end process;
end Ada_style;
The complete VHDL file test_reducer.vhd is available at www.
arithmetic-circuits.org.
The corresponding Ada version of the same procedure
(Algorithm D.1) is the following:

Algorithm D.2—Ada version
procedure nr_reducer(x, m: in integer; z: out integer)
is
function quotient(s: in integer; y: in natural) return
integer is
begin
if s < 0 then return -1; else return 1; end if;
end quotient;
y, s, r: integer;
begin
y := m*(2**(n-k));
s := x;
for i in 0 .. n-k loop