Page 21 - System on Package_ Miniaturization of the Entire System
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Preface






                          he System-on-Package (SOP) is an emerging system miniaturization technology
                          in contrast to System-on-Chip (SOC) at IC level and System-in-Package (SIP)
                    Tat module level. The SOC accomplishes miniaturization primarily by shrinking
                    lithographic dimensions from microscale in 1980s  to nanoscale currently. The
                    miniaturization in SIP is accomplished by thinning ICs from their original 800 micron
                    thick wafer dimensions to 50 microns and stacking as many as 10 of these, one on top
                    of the other, in 3D form. These are then interconnected by either wire bond or flipchip
                    technology. The SIP thus miniaturizes more than SOC. The recent Through Silicon Via
                    (TSV) developments further miniaturizes SIP by replacing flipchip with pad to pad
                    bonding. However, both SOC and SIP miniaturize a tiny part of the system since the
                    number of ICs or its size in a typical system such as a cellphone is a small fraction—
                    10–20% of the entire system. Therefore, both SOC and stacked SIP technologies,
                    address a small part of the total system.
                       This book introduces the SOP concept for miniaturizing the entire system. It argues
                    for the benefits of system miniaturization which include lower cost, higher electrical
                    performance and better thermo-mechanical reliability, than the current approach of
                    discrete component packaging. The SOP concept described in this book has two
                    fundamental drivers for miniaturization—1) reduction from three level hierarchy of IC,
                    package and board to a two- level hierarchy of IC and system package, which integrates
                    IC package and system board into one and 2) miniaturization of system components
                    from their current milliscale size discrete components to ultrathin-film embedded
                    components at micro to nano scale. The SOP concept proposes two locations for these
                    thin-film system components, one within the CMOS IC and the other in the system
                    package. In addition, the SOP makes a compelling case for what should be integrated
                    in CMOS and what components should be integrated in the system package, based on
                    optimized cost, performance, and functionality.
                       The Introduction to SOP  book is based on 12 years of research at Georgia Tech
                    Packaging Research Center (PRC), funded by the National Science Foundation (NSF)
                    under its Engineering Research Center (ERC) program, the State of Georgia, and more
                    than 100 companies from throughout the world. This research was performed by an
                    interdisciplinary team of 25 faculty and 500 graduate students from electrical,
                    mechanical, materials, and chemical engineering departments.
                        The SOP book is the first fundamental and technological book written to meet both
                    the industry and the academic needs. It tries to define, compare, and contrast the three
                    primary electronic system technologies namely, SOC, SIP, and SOP for their impact on
                    miniaturization, cost, electrical performance, and reliability. It has a total of 13 chapters

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