Page 264 - Mechanical Engineers' Handbook (Volume 2)
P. 264

References  253

                           during power-down, the data are held due to the floating gate. This technology has the
                           nonvolatility of the Antifuse with the programmability of the SRAM. Unfortunately, the on-
                           state resistance is higher than that of the Antifuse (before high voltage is applied) and the
                           programming time required is larger than the SRAM technology.



            REFERENCES
                           1. V. Betz and J. Rose, ‘‘How Much Logic Should Go in an FPGA Block?’’ IEEE Design and Test of
                             Computers, January–March 1998, pp. 10–15.
                           2. J. Anderson, J. Saunders, S. Nag, C. Madabhushi, and R. Jayaraman, ‘‘A Placement Algorithm for
                             FPGA Designs with Multiple I/O Standards,’’ paper presented at the International Conference on
                             Field-Programmable Logic and Applications (FPL), Villach, Austria, 2000, in Lecture Notes in Com-
                             puter Science, Vol. 1896, Springer-Verlag, pp. 211–220.
                           3. I. Cyliax, ‘‘Learning the Ropes: The FPGA Tour.’’ Circuit Cellular Online, Nov. 1999, www.
                             circuitcellular.com/online.
                           4. R. Patel, M. Wong, J. Costello, D. Reese, V. Bocchino, M. Chu, and J. Turner, ‘‘A 90.7 MHz-2.5
                             Million Transistors CMOS PLD with JTAG Boundary Scan and In-System Programmability,’’ in Proc.
                             IEEE Custom Integrated Circuits Conference, May 1–4, 1995, Santa Clara, California, pp. 507–510.
                           5. M. Ahrens, A. El Gamal, D. Galbraith, J. Greene, and S. Kaptanoglu, K. R. Dharmarajan, L. Hutch-
                             ings, S. Ku, P. McGibney, J. McGowan, A. Sanie, K. Shaw, N. Stiawalt, T. Whitney, T. Wong, W.
                             Wong, and B. Wu, ‘‘An FPGA Family Optimized for High Densities and Reduced Routing Delay,’’
                             in Proc. IEEE Custom Integrated Circuits Conference, May 13–16, 1990, San Jose, California, pp.
                             31.5.1–31.5.4.
                           6. H. Hsieh, W. Carter, J. Y. Ja, E. Cheung, S. Schreifels, C. Erickson, P. Freidin, and L. Tinkey, ‘‘Third-
                             Generation Architecture Boosts Speed and Density of Field-Programmable Gate Arrays,’’ in Proc.
                             Custom Integrated Circuits Conf., 1990, pp. 31.2.1–31.2.7.
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