Page 100 - A Practical Guide from Design Planning to Manufacturing

76 Chapter Three

In addition to targets for performance, cost, and power, software and
hardware support are also critical. Ultimately all a processor can do is
run software, so a new design must be able to run an existing software
base or plan for the impact of creating new software. The type of soft-
ware applications being used changes the performance and capabilities
needed to be successful in a particular product market.
The hardware support is determined by the processor bus standard
and chipset support. This will determine the type of memory, graphics
cards, and other peripherals that can be used. More than one processor
project has failed, not because of poor performance or cost, but because
it did not have a chipset that supported the memory type or peripherals
in demand for its product type.
For a large company that produces many different processors, how
these different projects will compete with each other must also be con-
sidered. Some type of product roadmap that targets different potential
markets with different projects must be created.
Figure 3-2 shows the Intel roadmap for desktop processors from 1999
to 2003. Each processor has a project name used before completion of the
design as well as a marketing name under which it is sold. To maintain
name recognition, it is common for different generations of processor
design to be sold under the same marketing name. The process genera-
tion will determine the transistor budget within a given die size as well
as the maximum possible frequency. The frequency range and cache size
of the processors give an indication of performance, and the die size gives
a sense of relative cost. The Front-Side Bus (FSB) transfer rate determines
how quickly information moves into or out of the processor. This will
influence performance and affect the choice of motherboard and memory.
Figure 3-2 begins with the Katmai project being sold as high-end
desktop in 1999. This processor was sold in a slot package that included
512 kB of level 2 cache in the package but not on the processor die. In
the same time frame, the Mendocino processor was being sold as a value
processor with 128 kB of cache. However, the Mendocino die was actu-
ally larger because this was the very first Intel project to integrate the
level 2 cache into the processor die. This is an important example of how
a larger die does not always mean a higher product cost. By including
the cache on the processor die, separate SRAM chips and a multichip
package were no longer needed. Overall product cost can be reduced even
when die costs increase.
As the next generation Coppermine design appeared, Katmai was
pushed from the high end. Later, Coppermine was replaced by the
Willamette design that was sold as the first Pentium 4. This design
enabled much higher frequencies but also used a much larger die. It
became much more profitable when converted to the 130-nm process
generation by the Northwood design. By the end of 2002, the Northwood