Page 13 - A Practical Guide from Design Planning to Manufacturing

Contents xi

Cache memory 143
Cache coherency 147
Branch prediction 149
Register renaming 152
Microinstructions and microcode 154
Reorder, retire, and replay 157
Life of an Instruction 160
Instruction prefetch 161
L2 cache read 162
Instruction decode 162
Branch prediction 162
Trace cache write 163
Microbranch prediction 163
Uop fetch and drive 163
Allocation 164
Register rename 165
Load instruction queue 165
Schedule and dispatch 165
Register file read 166
Execute and calculate flags 166
Retirement and drive 167
Conclusion 168
Key Concepts and Terms 168
Review Questions 168
Bibliography 169

Chapter 6. Logic Design 171
Overview 171
Objectives 171
Introduction 171
Hardware Description Language 173
Design automation 175
Pre-silicon validation 178
Logic Minimization 182
Combinational logic 182
Sequential logic 191
Conclusion 196
Key Concepts and Terms 197
Review Questions 197
Bibliography 197

Chapter 7. Circuit Design 199
Overview 199
Objectives 199
Introduction 199
MOSFET Behavior 200
CMOS Logic Gates 207
Transistor sizing 212