Page 157 - A Practical Guide from Design Planning to Manufacturing

130 Chapter Five

Cycle 1 2 3 4 5 6 7 8
Instr 1 Fetch Decode Execute Write
Instr 2 Fetch Decode Execute Write
Instr 3 Fetch Decode Execute Write
Instr 4 Fetch Decode Execute Write
Instr 5 Fetch Decode Execute Write
Instr 6 Fetch Decode Execute
Instr 7 Fetch Decode
Instr 8 Fetch
Figure 5-2 Pipelined processing.

every cycle. In reality, performance is significantly less than the ideal
because of pipeline breaks. Ideal pipeline performance would be possi-
ble only if every instruction could be executed in exactly the same
number of cycles and there were no dependencies between instructions.
However, some instructions are inherently more complex than others
and require more cycles of execution as a result. A divide operation
requires more cycles of computation than an add operation. Floating-
point operations require more cycles than integer operations. A load
that misses in the cache requires more cycles than one that hits.
Pipelining could still achieve ideal performance despite these varia-
tions in execution time if not for instruction dependencies.
Imagine that the first instruction is a divide, which stores its result
in register 2, and that the next instruction is an add instruction, which
reads register 2 as one of its inputs. This means that the add instruc-
tion cannot begin execution until the divide completes execution. This
causes a pipeline break or stall as shown in Fig. 5-3.

Cycle 1 2 3 4 5 6 7 8
Div R2, R1 Fetch Decode Execute Write
Add R3, R2 Fetch Decode Wait Execute Write
Instr 3 Fetch Decode Wait Execute Write
Instr 4 Fetch Decode Wait Execute
Instr 5 Fetch Decode Wait
Instr 6 Fetch Decode Wait
Figure 5-3 In-order pipeline data dependency.