Page 158 - A Practical Guide from Design Planning to Manufacturing

Microarchitecture 131

Cycle 1 2 3 4 5 6 7 8
Div R2, R1 Fetch Decode Execute Write
Add R3, R2 Fetch Decode Wait Execute Write
Branch Fetch Decode Wait Execute Write
Instr 4 Fetch
Figure 5-4 In-order pipeline control dependency.

The causes of pipeline breaks are as follows:

Data dependencies
Control dependencies
Resource conflicts

Because of the data dependency on instruction 1, instruction 2 and
all the following instructions are delayed. The pipeline will no longer
complete an instruction every cycle because for some cycles it will be
stalled while waiting for dependencies.
In addition to data dependencies, there are also control dependencies.
The execution of a branch instruction determines which instruction should
enter the pipe next. This means control dependencies cause breaks, stalling
not just the execution of the next instruction but even the fetch step. If the
third instruction were a branch, the pipeline might look like Fig. 5-4.
A third cause of pipeline breaks is resource conflicts. The microar-
chitecture of our processor may include only a single divider. If there are
two divide instructions to be executed, even without any data or control
dependencies, one may have to wait for the needed hardware to be avail-
able. Pipeline breaks limit how much speedup is achieved by pipelining.
The pipelines shown in Figs. 5-3 and 5-4 are called in-order pipelines
because the order that the instructions reach execution is the same as
the order they appear in the program. Performance is improved by
allowing instructions to execute out of order, improving the average
number of completed instructions per cycle (IPC).
Figure 5-5 shows an out-of-order pipeline, which starts as before with
a divide instruction and an add instruction that uses the result of the
divide. The fourth instruction is a multiply that uses the result of the add.
These instructions have data dependencies that require them to be
executed in order. However, the other instructions shown are subtracts,
which are independent of the other instructions. Each one does not
share its registers with any of the other instructions. This allows the first
subtract to be executed before the add instruction even though it comes
after it in the instruction flow.