Page 169 - A Practical Guide from Design Planning to Manufacturing

142 Chapter Five

for extremely specific sequences of instructions that happen to appear
in important benchmarks. These optimizations may not help real appli-
cations at all or may even be detrimental for most programs. There
have even been stories of compilers that turn on different optimizations
depending on whether the program file being compiled has the same
name as particular benchmark programs. To provide consistent results,
each benchmark must choose which compiler optimizations are allowed
by trying to pick those that could be used to achieve similar perform-
ance improvements for real programs.
Ultimately any benchmark measures not only processor performance
but also computer performance. It is impossible for the processor to run
any program at all without the support of the chipset and main memory,
but these components are also important in the overall computer per-
formance. A processor design that dedicates a large amount of die area to
cache may suffer relatively little performance loss when used with a slower
chip set or memory. Another processor that uses the same die area for more
functional units could potentially achieve higher IPC, but it is more
dependent upon the performance of the memory system. The computer
system used for the benchmarking could end up determining which of
these processors is rated as the fastest.
Huge sums of money are at stake when well-known benchmark results
are reported. There is enormous pressure on every company to make its
processors appear in the best possible light. To try and regain some con-
trol of how their products are measured, some companies create their own
benchmarks. Inevitably every company’s benchmarks seem to show their
own processors with higher relative performance than the benchmarks
created by any of their competitors. Unrealistic choices of benchmark
programs, complier optimizations, and system configurations are all pos-
sible ways to “cheat” benchmarks. Truly fair comparisons of performance
require a great deal of effort and continued vigilance to keep up with the
changing world of hardware and software.

Microarchitectural Concepts

Modern processors have used pipelining and increased issue width to exe-
cute more instructions in parallel. Microarchitectures have evolved to deal
with the data and control dependencies, which prevent pipelined proces-
sors from reaching their maximum theoretically performance. Reducing
instruction latencies is the most straightforward way of easing dependen-
cies. If results are available sooner, fewer independent instructions must
be found to keep the processor busy while waiting. Microarchitectures can
also be designed to distinguish between true dependencies, when one
instruction must use the results of another, and false dependencies,