Page 174 - A Practical Guide from Design Planning to Manufacturing

Microarchitecture 147

Cache coherency
Caches create special problems when multiple devices are sharing main
memory. Even in a computer system with a single CPU, other compo-
nents can access main memory. Graphics cards, peripherals, and other
hardware may read and write memory. When other devices read memory
it is important they get the latest value, which may exist only in the
processor cache. When other devices write memory it is important that
the data stored in the processor cache is kept current. In multiproces-
sor systems, there are multiple processors all sharing memory, each
with their own caches. The ability to keep all these caches synchronized
is called cache coherency.
The first requirement for supporting cache coherency is a bus proto-
col that supports snooping. Snooping is when an agent on the bus mon-
itors traffic to check whether it affects data in its own cache. A typical
bus protocol might support four phases per transaction, which are as
follows:

1. Request
2. Snoop
3. Response
4. Data

During the request phase the agent performing a read or write drives
request and address pins to indicate what data it will be accessing. The
snoop phase gives any agent sharing the bus the chance to check
whether its own cache is affected. The address from the request phase
must be compared with all the cache tags to determine if the data being
accessed is in the cache. If so, the snooping processor can provide the
data itself. If not, during the response phase the intended receiver can
signal that it is ready to send or receive data. The responder might signal
that it must defer the transaction. It does not have the data needed for
a read or is not ready to accept a write. The responder will create a new
transaction at a later time to satisfy this request. If the responder can
handle the transaction, then during the data phase, the actual data is
exchanged over the bus. Even when processors are idle and not execut-
ing any instructions, they must continue to snoop the bus to keep all the
caches synchronized.
In addition to snooping the bus, each processor must be able to keep
track of which lines in its cache are shared with other processors. It
would be inefficient to have to perform a bus transaction every single time
the cache is written just in case some other processor shares the data.
Instead, flags bits are associated with each line that track the ownership
of the data. The most common protocols have four ownership states.