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158   Chapter Five

        would never have fetched. There must be a way of discarding the improper
        results produced by these instructions. All the performance enhancing
        microarchitecture features work to improve performance while main-
        taining software compatibility. The true out-of-order nature of the
        processor must be concealed from the program, and the illusion of
        in-order execution maintained. The most common way to accomplish
        this is to use a reorder buffer (ROB).
          A reorder buffer takes out-of-order instructions that have completed
        execution and puts them back into the original program order. When
        instructions are being fetched and are still in order each one is allocated
        an entry in the ROB in the order the instructions are supposed to be exe-
        cuted. After the instructions are executed out of order, the ROB is updated
        to track which have been completed. The results produced by any instruc-
        tion are guaranteed to be correct only if all earlier instructions have
        completed successfully. Only at this point are the results committed and
        the instruction truly finished. This is called retiring an instruction.
          Before retirement any result produced by an instruction is specula-
        tive. New instructions will use the latest speculative result, but the
        most recent committed results must also be maintained in case the
        speculative results must be discarded. Only when an instruction retires
        are the committed results updated with that instruction’s result.
          Figure 5-18 shows an example of the ROB and the RAT at three dif-
        ferent moments in time as a set of three instructions is retired. The code



                                  Reorder buffer         Register alias table
                              Ready  Physical  Architectural
                             to retire  destination  destination  Physical  Architectural
                                                          register  register
         ADD R3, R2, R1  Oldest  No  R3      AX
           BNZ label           No     -       -            R10     AX
         SUB R6, R5, R4                                    R15     BX
                              Yes    R6      BX


                                                    Retired
                              Yes    R3      AX
         Add completes                                      R3     AX
                      Oldest   No     -       -
           execution                                       R15     BX
                              Yes    R6      BX


        Branch completes      Yes    R3      AX
                                                            R3     AX
            and was           Yes     -       -
          mispredicted                                     R15     BX
                      Oldest  Yes    R6      BX      X
                                                   Discarded
        Figure 5-18 Instruction retirement.
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