Page 405 - A Practical Guide from Design Planning to Manufacturing

Glossary 375

PTH Plated through hole.
P-to-N ratio The ratio of the PMOS transistor widths to NMOS transistor
widths in a CMOS logic gate. This ratio will determine what voltage level on
the input must be reached to switch the output of the gate.
P-type metal oxide semiconductor (PMOS) A MOSFET with P-type source
and drain terminals in an N-well. A PMOS transistor will conduct when the gate
voltage is low.
P-type semiconductor Semiconductor with acceptor dopants added to create
positive free charge carriers (holes).
Quad package A package with single rows of leads on four sides of the pack-
age. These packages typically have less than 250 total leads.
Random access memory (RAM) Semiconductor memory that allows stored
data to be read or written in any order. The mechanical movement of hard
drives or magnetic tapes requires data to be accessed in a specific order. Solid-
state memories do not have this limitation. The two basic types of RAM are
dynamic RAM (DRAM) and static RAM (SRAM).
Random access memory digital-to-analog converter (RAMDAC) The circuit
in a video adapter that scans the frame buffer RAM containing an encoded
image to be displayed and converts the binary values to analog voltages that
drive the monitor controls.
RAT Register alias table.
Reactive ion etch (RIE) An etch process that uses ions that will chemically
react with the material to be removed and an electric field to accelerate the ions
toward the surface of the wafer.
Read only memory (ROM) Semiconductor memory that can be read from but
not written to.
Real time clock (RTC) The computer circuit that tracks the passage of time
when the system is on or off. This is separate from the clock signals used to syn-
chronize communications between components.
Reduced instruction set computing (RISC) Computer architectures that support
only register or immediate operands in computation instructions, fixed instruction
size, and few addressing modes. Examples are SPARC and PA-RISC. See CISC.
Register alias table (RAT) Atable listing which physical registers are currently
holding the values of the architectural registers.
Register renaming The microarchitectural algorithm assigning architectural
registers to different physical registers in order to eliminated false data depend-
encies and improve performance.
Register transfer level (RTL) The level of abstraction of hardware description
language code, which models the cycle by cycle logic state of an integrated cir-
cuit but does not model the relative timing of different events within a cycle.
Register On-die storage for a single value on a processor.