Page 400 - A Practical Guide from Design Planning to Manufacturing

370 Glossary

Little endian A memory addressing format that assumes for numbers more
than 1 byte in size, the lowest memory address is the least significant byte (the
little end) of the number. See big endian.
Livelock When forward progress cannot be made in a program because mul-
tiple instructions repeatedly cause each other to be executed again.

Load instruction An instruction that moves data from a memory location to
a register.
Local oxidation of silicon (LOCOS) The formation of thermal oxide on only
parts of a silicon wafer by first covering regions where oxide is not wanted in a
layer of silicon nitride.
Logic bug A design flaw that causes an integrated circuit to produce a logi-
cally incorrect result.
Logic design The task of converting a microarchitectural specification into a
detailed simulation of cycle-by-cycle behavior using a hardware description language.
Low-pressure chemical vapor deposition (LPCVD) Deposition of material
through the chemical reaction of gases at low pressure. Low pressure allows good
control and creation of high-quality films but slows the deposition rate.

LSC Land side cap.
LVP Laser voltage probing.
Machine language The encoded values representing the instructions of par-
ticular computer architecture. Also called binary code. Any software must be con-
verted to machine language before being run on a processor.

MB megabyte.
MCH Memory controller hub.
MCM Multichip module.
MCM-C Multichip module with ceramic substrate.
MCM-D Multichip module with deposited substrate.
MCM-L Multichip module with laminate substrate.
Megabyte (MB) 2 20 or approximately 1 million bytes.
Memory controller hub (MCH) A chipset component controlling communica-
tion between the processor and main memory. Also called the Northbridge.
Memory hierarchy The use of progressively larger but slower levels of cache
memory to provide high storage capacity with low average latency.
MESI Modified, exclusive, shared, and invalid. The states of a typical cache
coherence protocol keeping track of how memory addresses are shared among
multiple cache memories.
Metal oxide semiconductor field-effect transistor (MOSFET) A transistor cre-
ated by a conducting wire resting on a thin layer of insulation deposited on top