Page 74 - Optical Switching And Networking Handbook
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                    SONET                                                                         59


                                       However, the signals are multiplexed one bit at a time into a DS-3
                                       signal using a DS-3 multiplexer (the M13). Because each DS-1 signal
                                       operates with its own clock, phase and frequency deviations may
                                       exist among the individual bit streams. This means that the bits can
                                       arrive early or late, in contrast to the other inputs. This is shown in
                                       Figure 3-3, which presents a conceptual view of the arrival sequence.




                                       Bit Stuffing


                                       To compensate for the potential problems and delays in the data
                                       arrival, the equipment must be capable of inserting a bit into an
                                       empty slot. This is called bit stuffing. The bits will be inserted into
                                       blank slots so that if a DS-1 line is slow to deliver the necessary bits,
                                       substitutes will be put in their place. This creates a scenario where
                                       the data can be aligned properly. Unfortunately, when we stuff these
                                       bits into a DS-3 data stream, the equipment at the receiving end can-
                                       not tell the difference between real data and fake data placed there
                                       to keep the slot occupied.Thus, the multiplexer does not know where
                                       to look for its reference point to find the DS-1 signals inside the DS-
                                       3 stream.To get back to the DS-1 signals, the entire DS-3 stream (all
                                       28 DS-1 signals) must be demultiplexed.This is time-consuming and
                                       expensive. Figure 3-4 illustrates the bit-stuffing process.








                                                                      Direction of data flow
                    Figure 3-4
                    Bits are “stuffed”
                    because the time
                    slots were empty.
                                         Timing Expected
                                        arrival of bit at center  1                    1
                                             line                       0        0
                                                     10 1 0  1 0  1  1 0  1 0  1 1  0 1  0 1 0  1 0  1 0  0
                                                                  S              S     S              S
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