Page 101 - Phase-Locked Loops Design, Simulation, and Applications

MIXED-SIGNAL PLL ANALYSIS Ronald E. Best 68
about one cycle of this oscillation; hence, it is reasonable to state that the lock-in time is

(3.62)

which is valid for any type of loop filter. T is also referred to as settling time.
L
Phase detector type 2. When the EXOR phase detector is chosen, the lock range can be
determined by considerations analogous to those made for the multiplier phase detector. We
assume the PLL is initially out of lock and that both signals u and u ′ are symmetrical
2
1
square waves. The reference frequency ω is offset from the center frequency ω ′ by Δω.
1 0
Then for u and u ′ we have
1 2

where U and U are the amplitudes of the square-wave signals. The phases θ and θ ′ are
10 20 1 2
then given by

The phase error θ therefore is
e

which is a ramp function. Checking Fig. 2.7 again, we note the average phase detector output
signal represents a triangular signal when the phase error ramps up linearly with time, its
peak amplitude being K π/2. Therefore, can be written as
d

where “tri” stands for “triangular waveform.” This signal is depicted in the upper trace
of Fig. 3.11. The average output signal of the loop filter is now given by

This signal is shown in the lower trace of Fig. 3.11. This signal modulates the frequency of
the VCO such that its peak deviation becomes

(3.63)

When the division ratio of the (optional) down scaler is N, the peak frequency deviation at