Page 123 - The Art of Designing Embedded Systems

110 THE ART OF DESIGNING EMBEDDED SYSTEMS

Yet it’s tough to probe modern surface-mount designs. Those tiny
whisker-thin pins are hard enough to see, let alone probe. Drink a bit of
coffee and you’ll dither the scope connection across three or four pins.
The most difficult connection problem of all is getting a good
ground. With speeds rocketing toward infinity the scope will show garbage
without a short, well-connected ground, yet this is almost impossible when
the IC’s pin is finer than a spiderweb.
So, when laying out the PCB add lots of ground points scattered all
over the board. You might configure these to accept a formal test point. Or,
simply put holes on the board, holes connected to the ground plane and
sized to accept a resistor lead. Before starting your tests, solder resistors
into each hole and cut off the resistor itself, leaving just a half-inch stub of
stiff wire protruding from the board. Hook the scope’s oversized ground
clip lead to the nearest convenient stub.
Figure on adding test points for the firmware as well. For example,
the easiest way to measure the execution time of a short routine is to tog-
gle a bit up for the duration of the function. If possible, add a couple of par-
allel YO bits just in case you need to instrument the code.
Add test points for the critical signals you know will be a problem.
For example:

Boot loads are always a problem with downloadable devices
(Flash, ROM-loaded FPGAs, etc.). Put test points on the critical
load signals, as you’ll surely wrestle with these a bit.
9 The basic system timing signals all need test points: read, write,
maybe wait, clock, and perhaps CPU status outputs. All system
timing is referenced to these, so you’ll surely leave probes con-
nected to those signals for days on end.
Using a watchdog timer? Always put a test point on the time-out
signal. Better, use an LED on a latch. You’ve got to know when
the watchdog goes off, as this indicates a serious problem. Simi-
larly, add a jumper to disable the watchdog, as you’ll surely want
it off when working on the code.
With complex power-management strategies, it’s a good idea to
put test points on the reset pin, battery signals, and the like.

When using PLDs and FPGAs, remember that these devices incor-
porate all of the evils of embedded systems with none of the remedies we
normally use: the entire design, perhaps consisting of tens of thousands of
gates, is buried behind a few tens of pins. There’s no good way to get “in-
side the box” and see what happens.