Page 128 - The Art of Designing Embedded Systems

Hardware Musings 1 15

that 1’11 need to generate some nastily complex waveform using a spare
output on the FPGA.
Some engineers figure that if they socket the programmable logic, they
can lift pins and tack wires to the dangling input or output. I hate this solu-
tion. Sometimes it takes an embarrassing number of tries to get a complex
PAL right-each time you must remove the device, bend the leads back to
program it, and then reinstall the mods. (An alternative is to put a socket in
the socket and lift the upper socket’s leads.) When the device is PLCC or an-
other, non-DIP package, it’s even harder to get access to the pins.
So I leave all unused inputs on these devices unconnected when
building the prototype, unfortunately creating a window of vulnerability to
SCR latchup conditions. Then it’s easy to connect mod wires to the un-
connected pins. When the first prototype is done I’ll change the schematic
to properly tie off the unused inputs so prototype 2 (or the production unit)
is designed correctly.
In years of doing this I have never suffered a problem from SCR
latchup due to these dangling pins. The risk is always there, lurking and
waiting for an unusual ESD or perhaps even a careless ungrounded finger
biasing an input.
I do tie spare gate inputs to ground, even with the first run of boards.
It just feels a little too dangerous to leave an unconnected 74HC74 lead
dangling. However, if at all possible, I have the person doing the PCB lay-
out connect these grounds on the bottom layer so that a few quick strokes
of the X-Acto knife can free them to solve another “whoops.”
In designs that use through-hole parts, by all means leave just a little
extra room around each chip so you can socket the parts on the prototype.
It’s a lot easier to pull a connected pin from a socket than to cut it free from
the board.

Clocks

For a number of years embedded systems lived in a wonderful era of
compatibility. Just about all the signals on any logic board were relatively
slow and generally TTL compatible. This lulled designers into a feeling of
security, until far too many of us started throwing digital ICs together
without considering their electrical characteristics. If a one is 2.4 volts and
a zero 0.7, if we obey simple fanout rules, and as long as speeds are under
10 MHz or so, this casual design philosophy works pretty well. Unfortu-
nately, today’s systems are not so benign.
In fact, few microprocessors have ever exclusively used TTL levels.
Surprise! Pull out a data sheet on virtually any microprocessor and look at