Page 130 - The Art of Designing Embedded Systems
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Hardware Musings  1 17


                        A better solution is to use clock-shaping logic near the processor it-
                   self. If the clock is generated a long way away, use a CMOS hysteresis cir-
                   cuit  (such as  a  74HCT14) to  clean  it  up.  The  extra  logic  adds delay,
                   though. If  your system requires clock synchronization, then use a special
                   low-skew clock driver made for that purpose.
                        In slower systems-under  20 MHz or so-I   prefer to design circuits
                   that don’t depend on a synchronous clock. What happens if you change to
                   a second sourced processor with  slightly different timing? Keep lots of
                   margin.
                        Never drive a critical signal such as clock off board without buffer-
                   ing. There are a very few absolutely critical signals in any system that must
                   be noise-free. Examine your design and determine what these are, and take
                   appropriate steps. Clock, of course, is the first that comes to mind. Another
                   is ALE (Address Latch Enable), used on processors with a multiplexed ad-
                   dresddata bus. A tiny bit of noise on ALE can cause your address register
                   to latch in the middle of a data cycle, driving an incorrect address to the
                   memories.
                        OK-so   now your voltage levels are right. Go back to the data sheet
                   and make sure the clock’s timing is in spec.
                        The 8088 requires a 33% clock duty cycle. Sure, it’s a little odd, but
                   this is a fundamental rule of nature to 8088 designers. Other chips have
                   tight duty cycle requirements as well.
                        Rise and fall times are just as important, though difficult to design
                   for. Some chips have minimum rise/fall time requirements! It’s awfully
                   hard to predict the rise/fall time for a track routed all over the board. That’s
                   one attraction of microprocessors with a clock-out signal. Provide a decent
                   clock-input to the chip, connect nothing to this line other than the proces-
                   sor, and then drive clock-out all over the board.
                        Motorola’s 68HC16 pulls a really neat trick. You can use a 32,768-
                   Hz standard watch crystal to clock the device. An internal PLL multiplies
                   this to 16 MHz or whatever, and drives a clock output to feed to the rest of
                   the board. This gets around many of the clock problems and gives a “free”
                   accurate time-of-day clock source.


                        Reset

                        The processor’s reset input is another source of trouble. Like clock.
                   some processors  have unusual  input voltage requirements  for reset. Be
                   wary.
                        Other chips require synchronous circuits. The old 2280 had a very
                   odd timing spec, clearly spelled out in the documentation, that everyone ig-
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