Page 127 - The Art of Designing Embedded Systems

1 14 THE ART OF DESIGNING EMBEDDED SYSTEMS

Unused Inputs
Once upon a time, back before CMOS logic was so prevalent, you
could often leave unused inputs dangling unconnected and reasonably ex-
pect to get a logic one. Still, engineers are a conservative lot, and most
were careful to tie these spare pins to logic one or zero conditions.
But what exactly is a logic one? With 74LS logic it’s unwise to use
Vcc as an input to any gate. Most LS devices will happily tolerate up to 7
volts on Vcc before something fails, while the input pins have an absolute
maximum rating of around 5.5 volts. Connecting an input to Vcc creates a
circuit where small power glitches that the devices can tolerate may blow
input transistors. It’s far better (when using LS) to connect the input to Vcc
through a resistor, thus limiting input current and yielding a more power-
tolerant design.
Modern CMOS logic in most of its guises has the same absolute
maximum rating for Vcc as for the inputs, so it’s perfectly reasonable to
connect input pins directly to Vcc-if you’re sure that production will
never substitute an LS equivalent for the device you’ve called out.
CMOS does require that every unused input be pulled to a valid logic
zero or one to avoid generating an SCR latchup condition.
Fast CMOS logic (like 74FCT) switches so quickly, even at very low
clock rates, that glitches with Fourier components into billions of cycles
per second are not uncommon. Reduce noise susceptibility by tying your
logic zeroes and ones directly to the power and ground planes.
And yet . . . one must balance the rules of good design with practical
ways to make a debuggable system. A thousand years ago circuits used
vacuum tubes mounted on a metal chassis. All connections were made by
point-to-point wiring, so making engineering changes during prototype
checkout must have been pretty easy. Later, transistors and ICs lived on PC
boards, but incorporating modifications was still pretty simple. Now we’re
faced with whisker-thin leads on surface-mount components, with 8- and
10-layer boards where most tracks are buried under layers of epoxy and out
of reach of our X-Acto knives. If we tie every unused input, even on our
spare gates, to a solid power or ground connection, it’ll be awfully hard to
cut the connection free to tie it somewhere else. Lifting the pins on those
spare gates might be a nightmare.
One solution is to build the prototype boards a little differently than
the production versions. I look at a design and try to identify areas most
likely to require cutting and pasting during checkout. A prime example is
the programmable device-PALS or FPGAs or whatever. Bitter experi-
ence has taught me that probably I’ll forget a crucial input to that PAL, or