Page 174 - The Art of Designing Embedded Systems

Troubleshooting Tools 16 1

signals to an idle, nonactive state. This confuses the state machine used in
the synchronous timing circuits, though; generally the state machine will
not recover properly when emulation resumes, and thus generates incorrect
reads and writes.
Most emulators cannot afford to completely idle the bus, anyway, as
it’s important to echo DMA and refresh cycles to the target system at all
times.
Since the processor in the ICE usually runs a little control program
when sitting still at a breakpoint, another option is to echo these readlwrite
cycles to the bus. That keeps the state machine alive, but destroys the in-
tegrity of the user’s system because internal emulator write cycles trash
user memory and YO.
Another possibility is to echo the cycles, but fake out write cycles.
When the emulator’s CPU issues a write, the ICE drives an artificial read
to the target. Unhappily, on many chips read and write cycles have some-
what different timing, which may confuse the user’s state machine.
None of these solutions will work on all CPUs and in all user sys-
tems. If you really feel compelled to use a synchronous memory design.
talk to the emulator vendor and see how they handle cycle echoing at a
breakpoint.
Consider adding an extra input to your state machine that the emula-
tor can drive with its “stopped” signal and that shuts down memory reads
and writes. Talk timing details with the vendor to ensure that their
“stopped” output comes in time to gate off your logic.

Add Debugging Resources

Debugging always steals too much time from the schedule. This fact
implies that we’ve got to anticipate problems when designing the hard-
ware, and take every action possible to ease troubleshooting.
Always-unless your system is so cost constrained that a buck is a
huge deal-add an extra output port to the system, one dedicated just to de-
bugging. Why?
As we saw in Chapter 4, a very effective and inexpensive way to
measure system performance is to instrument your code. Add a
line that sets a bit-on this YO port-high when in an ISR to mea-
sure ISR time. Diddle another YO bit in the idle loop to measure
overall system loading.
Toggle one of the bits when the system resets. As I said in Chap-
ter 6, a watchdog time-out is a serious event. If your system auto-