Page 92 - The Art of Designing Embedded Systems
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Real Time Means Right Now!  79


                        Learn about your hardware. Pure software types often have no idea
                   that  the CPU is actively  working  against them.  I talked  to  an engineer
                   lately who was moaning about how slow his new 386EX-based instrument
                   runs. He didn’t know that the 386EX starts with 3 1 wait states and so had
                   never reprogrammed it to a saner value.


                        A Poor Man‘s Perfomrance Analyzer
                        Do keep in tune  with the embedded tool industry’s wide range of
                   performance-analyzing  devices. But don’t fail to take detailed measure-
                   ments just because such a tool is not available. An oscilloscope coupled
                   to a few spare output bits can be a very effective and cheap performance
                   analyzer.
                        Whether  you’re  working  on  an  8-bit  microcontroller  or a  32-bit
                    VME-based system, always dedicate one or two parallel YO  bits to de-
                   bugging. That is, have the hardware designers include a couple of output
                   bits just for sofrware debugging purposes. The cost is vanishingly small;
                   the benefits often profound.
                        Suppose you’d like to know an ISR’s (or any other sort of routine’s)
                   precise execution time. Near the beginning of the routine set a debug out-
                   put bit high; just before exiting return the bit to a zero. For example:
                        ISR-entry:
                             push all registers
                             set output bit high
                             service interrupt
                             reset output bit
                             pop registers
                             return
                        Put one scope probe on the bit. You’ll see a pattern that might re-
                    semble that in Figure 4-8. The ISR is executing when the signal is high.
                        In this example we  see two invocations  of  the ISR. The first time
                    (note that the time base setting is 2 msec/division), the routine runs for a bit
                   over  3  msec.  Next  time  (presumably  the  routine  includes  conditional
                   code), it runs for under 1 msec.
                        We also clearly  see a  14-msec period between executions. If these
                    two samples are indicative of the system’s typical operation, the total CPU
                   overhead dedicated to this one interrupt is (3 msec+l  msec)/l4 msec. or
                   29%.
                        Crank up the scope’s time base and you can measure the ISR’s exe-
                   cution time to any desired level of precision.
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