Page 317 - ARM 64 Bit Assembly Language

306 Chapter 9

• The mode can be one of a, m, n, p,or z, to specify the rounding mode.
• Rd and Rn can be any AArch64 integer register.
• Fd and Fn can be any single or double precision register.

9.6.2.2 Operation

Opcode Effect Description
fcvt<mode>s Rd ← int(Fn) Convert float to signed integer.
fcvt<mode>u Rd ← uint(Fn) Convert float to unsigned integer.
scvtf Fd ← float(Rn) Convert signed integer to float.
ucvtf Fd ← uf loat(Rn) Convert unsigned integer to float.

9.6.2.3 Examples

1 fcvtas d5, x7 // Convert signed 64-bit integer to double
2 fcvtpu d0, w4 // Convert unsigned 32-bit integer to double
3 fcvtas s0, x7 // Convert signed 64-bit integer to single
4 ucvtf x3, d0 // Convert double to unsigned integer

9.6.3 Convert between fixed point and floating point

VFPv3 and higher coprocessors have additional instructions used for converting between
fixed point and single precision floating point. The AArch64 instructions are:

fcvtzs Convert Float to Signed Fixed Point.
fcvtzu Convert Float to Unsigned Fixed Point.
scvtf Convert Signed Fixed Point to Float.
ucvtf Convert Unsigned Fixed Point to Float.

9.6.3.1 Syntax

fcvtz<s|u> Rd, Fn, #fbits
<s|u>cvtf Fd, Rm, #fbits

• The fcvtz instructions always round towards zero.
• The cvtf instructions always round using the FPCR rounding mode.
• Rd and Rn can be any AArch64 integer register.