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CHAPTER 10

                     Advanced SIMD instructions



                     In addition to the FP/NEON instructions described in the previous chapter, AArch64 also
                     supports Advanced SIMD instructions, which allow the programmer to treat the FP/NEON
                     registers as vectors (arrays) of data. Advanced SIMD uses the same set of registers described
                     in Chapter 9, but adds new views to provide the ability to access the registers in more ways.
                     Advanced SIMD adds about 125 instructions and pseudo-instructions to support not only
                     floating point, but also integer and fixed point.

                     A single Advanced SIMD instruction can operate on up to 128 bits, which may represent
                     multiple integer, fixed point, or floating point numbers. For example, if two of the 128-bit
                     registers each contain eight 16-bit integers, then a single Advanced SIMD instruction can add
                     all eight integers from one register to the corresponding integers in the other register, resulting
                     in eight simultaneous additions. For certain applications, this vector architecture can result in
                     extremely fast and efficient implementations. Advanced SIMD is particularly useful at han-
                     dling streaming video and audio, but also can give very good performance on floating point
                     intensive tasks.

                     The 32 FP/NEON/Advanced SIMD registers, originally introduced in Chapter 9, can be
                     accessed using various views. Some SIMD instructions use the byte, half-word, word,
                     and double-word views from Chapter 9, but most of them use the Advanced SIMD views.
                     Fig. 10.1 shows the different ways of viewing an Advanced SIMD register. Each register can
                     be viewed as containing a vector of 2, 4, 8, or 16 elements, all of the same size and type. Indi-
                     vidual elements of each vector can also be accessed by some instructions. The scalar register
                     names and views introduced in Chapter 9 are also used by some instructions. A scalar can be
                     8 bits, 16 bits, 32 bits, or 64 bits. The instruction syntax is extended to refer to elements of a
                     vector register by using an index, x. For example Vm.4s[x] is element x in register Vm,where
                     Vm is treated as a vector of four single-word (32-bit) elements.



                     10.1 Instruction syntax

                     The syntax of Advanced SIMD instructions can be described using an extension of the nota-
                     tion used throughout this book. Each instruction operates on certain types of register(s), and
                     there are many registers. Advanced SIMD instruction syntax may use any of the following
                     register definitions:


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