Page 335 - ARM 64 Bit Assembly Language
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Advanced SIMD instructions 325

                     Xy          Refers to a 64-bit AArch64 integer register.
                     Wy          Refers to 32-bit AArch64 integer register.
                     By          Refers to the lower 8-bits, or byte, of an Advanced SIMD register.
                     Hy          Refers to the lower 16-bits, or half-word, of an Advanced SIMD register.
                     Sy          Refers to the lower 32-bits, or single-word, of an Advanced SIMD register.
                     Dy          Refers to the lower 64-bits, or double-word, of an Advanced SIMD register.
                     Fy          Is used to indicate either a single-word or double-word FP/NEON register. F
                                 must be either s for a single word register, d for a double word register.
                     Vy          A 128-bit Advanced SIMD register. y can be any valid register number.
                     Vy.T        A 128-bit Advanced SIMD register, treated as a vector of elements of type T,
                                 where T may be one of:
                                 b A vector of 16 bytes.
                                 h A vector of 8 half-words.
                                 s A vector of 4 words.
                                 d A vector of 2 double-words.
                                 Some instructions can only allow a subset of these types.
                     Vy.nT       A 128-bit Advanced SIMD register, or the lower 64 bits of an Advanced SIMD
                                 register, treated as a vector of elements of type T,where T may be one of:
                                 16b A 128-bit Advanced SIMD register, treated as a vector of sixteen bytes.
                                 8b The lower 64 bits of an Advanced SIMD register, treated as a vector of eight
                                  bytes.
                                 8h A 128-bit Advanced SIMD register, treated as a vector of eight half-words.
                                 4h The lower 64 bits of an Advanced SIMD register, treated as a vector of four
                                  half-words.
                                 4s A 128-bit Advanced SIMD register, treated as a vector of four words.
                                 2s The lower 64 bits of an Advanced SIMD register, treated as a vector of two
                                  words.
                                 2d A 128-bit Advanced SIMD register, treated as a vector of two double-words.
                                 Some instructions can only allow a subset of these types.
                     Vy.nT[x] Element x of an Advanced SIMD register, treated as a vector of type nT.
                     Each instruction has its own set of restrictions on legal values for the registers and types used.
                     For example, one possible form of the mov instruction is:
                     mov Vd.T[x],Wn

                     which indicates that a 32-bit AArch32 register is used as the source operand, and any element
                     of any Advanced SIMD register may be used as the destination. However, the instruction fur-
                     ther requires that T must be either 2s or 4s, in order to match the size of Wn.

                     Instructions may have several forms. In those cases, the following syntax is used to specify
                     possible forms:
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