Page 338 - ARM 64 Bit Assembly Language

P. 338

328 Chapter 10

• <list> speciﬁes the list of registers. There are four list formats:
1. {Vt.T}
2. {Vt.T, V(t+1).T} or {Vt.T-V(t+1).T}

3. {Vt.T, V(t+1).T, V(t+2).T} or {Vt.T-V(t+2).T}
4. {Vt.T, V(t+1).T, V(t+2).T, V(t+3).T} or {Vt.T-V(t+3).T}
The registers must be consecutive. Register 0 is consecutive to register 31.
• T must be b, h, s,or d.
• The immediate index speciﬁes which element of each register is to be used, and must be
appropriate for the data size speciﬁed by T. The same element will be used for all regis-

ters.
• Xn is the AARCH64 register containing the base address.
• Xm is the AARCH64 register containing an offset.
• If a register or immediate offset is given, then the base register, Xn, will be post-
incremented.
• The post-increment immediate offset, if present, must be 8, 16, 24, 32, 48, or 64, depend-
ing on the number of elements transferred and the size speciﬁed by T.

10.2.1.2 Operations

Name Effect Description
ld<n> tmp ← Xn Load one or more data items into a
incr ← byteSize(T) single lane of one or more registers.
for V ∈ regs(<list>) do
V [index]← Mem[tmp]
tmp ← tmp + incr
end for
if #imm is present then
Xn ← Xn + imm
else
if Xm is speciﬁed then
Xn ← Xn + Xm
end if
end if
continued on next page

333 334 335 336 337 338 339 340 341 342 343