Page 340 - ARM 64 Bit Assembly Language

330 Chapter 10

• <op> must be either ld or st.
• <n> must be one of 1, 2, 3,or 4.
• <list> specifies the list of registers. There are four list formats:
1. {Vt.T}
2. {Vt.T, V(t+1).T} or {Vt.T-V(t+1).T}
3. {Vt.T, V(t+1).T, V(t+2).T} or {Vt.T-V(t+2).T}

4. {Vt.T, V(t+1).T, V(t+2).T, V(t+3).T} or {Vt.T-V(t+3).T}
The registers must be consecutive. Register 0 is consecutive to register 31.
• T must be 16b, 8b, 8h, 4h, 4s, 2s,or 2d.If <n> is 1, then T can be 1d.
• Xn is the AARCH64 register containing the base address.
• Xm is the AARCH64 register containing an offset.
• If a register or immediate offset is given, then the base register, Xn, will be post-
incremented.
• The post-increment immediate offset, if present, must be 8, 16, 24, 32, 48, or 64, depend-
ing on the number of elements transferred and the size specified by T.

10.2.2.2 Operations

Name Effect Description
ld<n> tmp ← Xn Load multiple structures into all lanes
incr ← byteSize(T) of one or more registers.
for 0 ≤ x< nLanes(T) do
for V ∈ regs(<list>) do
V[x]← Mem[tmp]
tmp ← tmp + incr
end for
end for
if #imm is present then
Xn ← Xn + imm
else
if Rm is specified then
Xn ← Xn + Xm
end if
end if
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