Page 115 - Analog Circuit Design Art, Science, and Personalities

Analog Design Discipline

pretty creative type, saw a way to reduce the area occupied by the diodes by making
a change in their geometry. This should immediately have raised a flag, if for no
other reason than last minute changes are always dangerous. The specified diode
geometries were proven to work in previous chips; the new ones should have worked
as well, but they couldn’t know absolutely, positively for sure until the IC came out.
But. maybe our analog designer had something else on her or his mind that day, or
just didn’t feel the need to play “what if” in this case-after all, they’re only diodes. . .
So the designer gave the green light for the change and proceeded to completely
forget about it. But the diodes didn’t forget. They had been turned into quite differ-
ent devices and had different laws to obey when they were turned on.
During the layout of an IC (or in a discrete circuit, of a printed circuit board), the
analog circuit designer usually has a little free time since the design is, in theory,
finished. There might be a temptation to work on a different project for fill-in; resist
it. There is still plenty to focus on for the circuit in layout. First and foremost, the
designer must check with the mask designer daily to make sure that the circuit
being laid out is in fact the same circuit that was breadboarded and simulated. Any
layout parasitics that might affect the operation of the circuit should be immediately
incorporated into the simulation or breadboard to ascertain their effects. Any devia-
tion from the specified device geometries or placement (such as in our diode string)
should be thoroughly investigated. If there is any doubt, don’t do it!
The most common IC layout parasitic is interconnect resistance, since metal
interconnect lines can easily reach tens of ohms. and polysilicon lines thousands of
ohms of resistance. Relatively small voltage drops along supply and ground lines
can easily upset sensitive bipolar analog biasing, where a mere 3 mV drop can
cause more than 10% change in current. If there is any doubt about the effect of a
parasitic resistance, place a like-valued resistor in the breadboard or simulation and
see what effect it has. Close behind in problematic effects are parasitic capacitance
and inductance. And don’t overlook mutual inductance between IC wirebonds or
package leads. I once had a 45 MHz I.F. amplifier in which the pad arrangement
was completely dictated by inductive coupling.
Also during the layout phase, more questions should be asked about the circuit (if
they haven’t been asked already). Questions like: What happens when an input or
output is shorted to ground or supply? For an IC, what will the planned pinout do if
the device is inserted backwards in the socket? Can adjacent pins be shorted to each
other? In many cases, the answer to such questions may be, “it blows up.” That’s
okay because it is still information gained, and the more the designer knows about
the circuit, the better. And often, by asking some of these questions at this time, some
surprisingly simple changes in layout may improve the ruggedness of the circuit.
Finally, the analog designer should also be planning ahead for evaluation of the
new circuit when it comes out. While the original specifications for the project will
define much of the testing required, the evaluation phase should definitely exercise
the circuit over a wider range. During the evaluation phase. tests should be imple-
mented to answer such questions as: How does the circuit “die” as the supply is
reduced below the minimum operating voltage? Will the circuit survive a momen-
tary overvoltage? What happens outside of the operating temperature range? What
effect will loads other than those for which the circuit was designed have? These
sorts of tests can pay big dividends by exposing a problem lurking just outside the
normal operating “envelope” of the circuit.
Before I became involved in the FET driver project, the circuit had already been
through the critical layout phase not once but twice, with several additional minor
mask changes in between. The too brief evaluations of each new version, no doubt

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