Page 117 - Anatomy of a Robot
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03_200256_CH03/Bergren  4/17/03  12:27 PM  Page 102
                             102 CHAPTER THREE
                               The major advantage of a uCoded CISC machine is in the richness of the instruction
                             set. Many of the CISC machine designers provide specialized instructions that can be
                             of  great  use  in  specific  circumstances.  Some  CISC  computers  will  have  specific
                             instructions for the treatment of continuous streams of data such as might come from
                             communication  interfaces. This  becomes  almost  a  crossover  capability  from  DSP
                             machines. If the robot needs specialized communication or data-processing instruc-
                             tions, look for them in the CISC instruction set of the processors under consideration.
                                    ™
                             Pentium processors have the Multimedia Extensions (MMX) instruction sets and cer-
                             tain constructs that are good for the processing of vector data.
                               Some CISC machines provide floating-point instructions, which can greatly speed
                             up some algorithms. Others provide communication instructions such as the computa-
                             tion of ECC polynomials and Viterbi codes.



                             COPROCESSORS
                             In an effort to provide extra horsepower for their processors, some designers couple
                                                         ™
                             processors together. The Pentium class processors can operate in tandem. This allows
                             the same programs to operate a bit faster without significant modifications. For more
                             information, go to www.intel.com/products/server/processors/server/xeon_mp/index.
                             htm?iid=search+XeonMP.
                               Other  designers  coupled  together  processors  with  disparate  capabilities.  The
                             PowerPC ™  from  Motorola  is  in  such  a  class. The  second  processor  is  termed  the
                             communications processor and is reserved almost exclusively for the use of Motorola
                             processor designers to provide communication processing. It’s a simple RISC machine
                             that is not documented for end users. It’s used, for instance, to provide the processing
                             necessary to implement LAN (local area network) communication interfaces. The com-
                             munication processor can handle several communication interfaces at the same time,
                             limited only by the overall bandwidth of the coprocessor. Other communication proto-
                             cols like ATM, Sonet, and others are available as complete uCode that can be loaded into
                             the coprocessor and kicked off.
                               If we can find a processor with significant coprocessing power, it can be used for par-
                             allel processing. The newly introduced network processors can be used like this. They
                             are basically multiple RISC processors in a single chip. They’re used for the process-
                             ing of packets on the Internet, a task that can be partitioned and requires great horse-
                             power. These chips are available from Vitesse, IBM, Motorola, and many others. Thus
                             far, they have been used only for network processing, which handles IP packets in real
                             time, but they are very powerful parallel processing machines and might work well in
                             a robot control system.
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