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COMPUTER HARDWARE 99
many different computers, some of which have few GP registers. If we have specific
software routines (like loops in the robot’s control system software) that we want to
speed up, we can pay specific attention to that small area of code. Often, with C lan-
guage statements, such as the register construct, we can force the compiler to generate
code that will use the faster GP registers during computation. We still have to examine
the intermediate assembly code to make sure we are getting the results we desire.
Certainly, if the robot’s code is written in assembly code, we can force the issue much
more easily. The point is, consider the internal register structure of the computer when
picking the computer or designing the software.
Second, be advised that some computers have more computational hardware than
others. All computers have fixed-point computational capabilities, and some have float-
ing-point capabilities as well. Others, as we have discussed, have very special-purpose
compute units with DSP or communication hardware built in. Again, take a close look
at the computer requirements.

INSTRUCTION SET

An instruction set is the base language of the computer. These are generally word-
length, assembly language words that the computer can look at to understand what it
must do during the execution of a program. It does not matter whether the program is
written in C, Forth, C , Fortran, or assembly language. The compilers and assem-
blers always must reduce the program to a series of instruction-set commands that the
computer can execute. In assembly language, they look something like this:
ADD r0, r1 (Add GP register 0 to GP register 1)
SUB r2, r3 (Subtract GP register 2 from GP register 3)
When translated to binary, they would reside in instruction words like this (to use an
imaginary 8-bit computer instruction set):

Bit 7 6 5 4 3 2 1 0
OpCode x x x x
Source register x x
Destination register x x
where the OpCodes are
0000 for add
0001 for subtract and so on
ADD r0, r1 codes as 0 0 0 0 0 0 0 1
SUB r2, r3 codes as 0 0 0 1 1 0 1 1