Page 110 - Anatomy of a Robot

03_200256_CH03/Bergren 4/17/03 12:27 PM Page 95
COMPUTER HARDWARE 95
computer from scratch, be very careful to analyze the timing of the DRAM signals. If
they are even off a little from the requirements, errors can occur that will be hard to
isolate.
To use DRAM properly, we have to look into its internal construction. DRAM is
commonly built as an array of bits. If a million bits (1,024 1,024 1 million) are
inside the DRAM, the bits may well be arranged as 1 large array with 1,024 columns,
each of which has 1,024 bits in a row. The address lines coming into the DRAM gen-
erally are timeshared. To address 1 million bits inside the DRAM, 20 address bits are
20
required (2 1 million). Instead of having 20 address pins on the DRAM, it likely
only has 10, and they are used twice in the following manner.
The first 10 bits of the address are presented to the DRAM. These 10 address bits can
address an entire row of bits within the memory array. This cycle is called RAS for Row
Address Select. During this time period, the entire addressed row of 1,024 memory bits
is read into a RAS read register inside the DRAM. Next, the computer chip provides
the remaining 10 address bits at the address input pins of the DRAM during what’s
called the CAS cycle for Column Address Select. During the CAS cycle, only one of the
1,024 memory bits from the RAS read register is sent to the DRAM output pin. This is
the RAS/CAS cycle. This type of architecture saves a great deal of space and circuitry
inside the DRAM and has become a standard in the computer industry.
The timing of all the DRAM signals must be very precise to avoid errors. Most com-
puter chips on the market will drive DRAM directly with default timing known to work
with contemporary DRAM. Most computer chips also have registers within them that
can be used to change the default timing on the computer chip’s DRAM interface pins.
One of the interesting benefits of the RAS/CAS cycle is that, in our example, 1,024
bits are fetched at the same time during the RAS cycle. It’s only a preference that we hap-
pen to want only one bit during the CAS cycle. The truth is, if we run multiple CAS
cycles after the single RAS cycle, we can fetch many bits out of the RAS read register.
This method of using DRAM is generally called page mode, and not all DRAM supports
it. The next section dealing with cache memory will illustrate a good use for this feature.
DRAM comes in many different styles, each with a different acronym. They each
have different timing and power requirements. For further study, check out www.
arstechnica.com/paedia/r/ram_guide/ram_guide.part1-1.html and www.howstuffworks.
com/ram.htm.

CACHE MEMORY

Great, just when we thought we had this memory thing licked, along comes another
kind. Cache memory (pronounced “cash”) is a small amount of memory within the
computer chip that greatly speeds up the execution of a program. The central idea is that