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COMPUTER HARDWARE 97
way, the cache data remains the same as the contents of the DRAM. An article at
www.pcguide.com/ref/mbsys/cache/func_Write.htm describes writing to cached mem-
ory locations. Follow all the links for a complete explanation.
The cache controller must recognize when it must act while the computer is access-
ing a DRAM address. The most complex method is to store the DRAM address inside
the cache memory. The cache controller must then have address-matching hardware that
can compare the computer-generated DRAM address with all the addresses within the
cache memory bank. This type of hardware is expensive and is generally known as
Content Addressable Memory (CAM). A less expensive alternative is simply to cache
only within a small address range. If the computer can cache all the DRAM data that
resides within a certain memory address range, things are simplified. The cache con-
troller need only compare the upper bits of the computer-generated DRAM address with
the address of the cached memory range. The cache memory controller and how it rec-
ognizes situations where it comes into play are discussed at www.pcguide.com/ref/
mbsys/cache/func_Mapping.htm.
Cache memory can reside in a few different places. If it’s inside the processor chip,
it’s generally termed a Level One (L1) cache. It’s the fastest and, because it’s inside the
computer chip, it’s generally the smallest and most expensive.
Board designers can also put cache memory chips between the computer chip and
the DRAM. This cache, external to the processor chip, is generally called a Level Two
(L2) cache. Sometimes the L2 cache is also inside the computer chip. The L2 cache is
slower than L1, but it is often bigger. The cache controller looks to the L1 cache first.
If the L1 cache does not have the data, the cache controller looks to the L2 cache. If the
L2 cache does not have the data, the cache controller goes to the DRAM.
The following web sites help define L1 and L2 caches. Follow all the links; there is
much more to learn:

www.pcguide.com/ref/mbsys/cache/
www.pcguide.com/ref/mbsys/cache/role.htm
www.pcguide.com/ref/mbsys/cache/layers.htm
www.pcguide.com/ref/cpu/arch/int/comp_Cache.htm
www.computerhope.com/jargon/l/l1.htm
www.computerhope.com/jargon/l/l2.htm

Cache Thrashing
As we’ve seen, cache memory is most effective when the computer program loops in a
small local loop, a portion of the program confined to a small number of DRAM mem-
ory addresses that can all reside in a cache at the same time. It is possible to misuse