Page 102 - Building A Succesful Board-Test Strategy

88 BUILDING A SUCCESSFUL BOARD-TEST STRATEGY

If ROMs, RAMs, and their corresponding buses have passed, the test checks
the board's I/O. I/O tests can be simple or complex, depending on the situation.
Steps include reading AID converter output values, reading and setting parallel
bits, and examining complex devices such as direct-memory-access (DMA)
channels. In some cases, obtaining meaningful data from I/O devices can require
programming dozens of internal registers. Therefore, many emulation testers
offer overlay RAM, which overrides on-board memory during test execution. This
approach allows examining board logic, for example by triggering I/O initializa-
tion routines, regardless of any memory faults.
Digital word generators resemble the memory-and-state-machine archi-
tecture of emulators, but provide a more general-purpose solution. Like the emu-
lator, they store stimulus and response signals in local memory. They also include
several types of fixed-logic-level channels, but add some programmable channels
as well. Channels again exist as groups, and the tester can control them only as
groups. However, you can add or configure signal channels by buying additional
modules from the tester manufacturer. This architecture offers more flexibility
than the emulators do. Nevertheless, timing flexibility is similarly limited, and
programmable timing and test speed is limited to the time necessary to perform
one memory-access cycle.
Most sophisticated in the digital-test arsenal is the performance functional
tester. This system tests the board operation to established specifications, rather
than "merely" controlling it. The tester can emulate the board-to-system interface
as closely as possible to ensure that the board will work in the final system without
actually installing it.
This alternative offers highly flexible digital channels, as well as individually
selectable logic levels (to serve several logic families on the same board), timing,
and control. To synchronize the test with analog measurements, the tester often
includes special circuitry for that purpose. Subject to the tester's own specifications
(we will discuss this subject further in Chapter 8), it can precisely place each signal
edge. Programs are divided into clock cycles, rather than events, permitting more
direct program development through interface with digital simulators.
Conventional stimulus/response functional testing relies on simulation for
test-program development. As boards become more complex, however, program-
mers must trade off test comprehensiveness against simulation time. Design or test
engineers who understand board logic often select a subset of possible input pat-
terns to reduce the problem's scope. After obtaining fault-coverage estimates from
a simulator using that subset, engineers can carefully select particular patterns from
the subset's complement to cover additional faults.

2.3.11 Finding Faults with Functional Testers
Once a board fails functional test, some kind of fault isolation technique
must determine the exact reason, either for board repair or for process improve-
ment. Common techniques include manual analysis, guided-fault isolation (GFI),
fault dictionaries, and expert systems.