Page 98 - Building A Succesful Board-Test Strategy

84 BUILDING A SUCCESSFUL BOARD-TEST STRATEGY

« Levels: Voltage and current values assigned to logic values in the pattern
data. Levels may vary over the board, depending on the mix of device
technologies.
» Flow control: Program tools that specify loops, waits, jumps, and other
sequence modifiers

The simplest type of digital functional "tester" is an I/O port. It offers a
limited number of I/O channels for a board containing a single logic family. The
I/O port offers a low-cost solution for examining a few digital channels. However,
it is slow and provides little control over timing or logic levels during test, severely
limiting its capability to verify circuits at-speed or to-spec.
Emulators exploit the fact that many digital boards feature bus-structured
operation and resemble one another functionally. A somewhat general, hardware-
intensive test can verify those common functions, reducing overall test-
development effort. Emulation replaces a free-running part of the board's logic
with a test pod. It then mimics the board's behavior in the target system, stopping
at convenient points to examine registers and other hardware states. Figure 2-28
shows a simplified block diagram of a typical emulation tester.
Emulation is perhaps the least well-understood test technique. One problem
is that many sources refer to it as in-circuit emulation, yet it has nothing to do with
in-circuit testing. Calling it performance testing, as other sources do, better
describes its operation.
There are three basic types of emulation. Most familiar is microprocessor
emulation, where a test pod attaches to the microprocessor leads or plugs into an
empty microprocessor socket. On boards with more than one processor, the test
must replace all of them, either serially or simultaneously. A successful test requires
that the board's power and clock inputs, reset, data-ready, and nonmaskable inter-
rupts function correctly.
Memory emulation replaces RAM or ROM circuitry on the board under test,
then executes a stored program through the existing microprocessor and sur-
rounding logic, including clock, address and data buses, address decoder, and
RAM. Because the microprocessor remains part of the circuit, this variation has
advantages over microprocessor emulation for production test. Also, the tester does
not require a separate pod for each microprocessor, only one for each memory
architecture, reducing hardware acquisition and development costs.
Bus-timing emulation does not actually require the presence of a micro-
processor on the board at all. It treats the processor as a "black box" that simply
communicates with the rest of the board logic over I/O lines. The bus can be on
the board or at the edge connector. The technique executes MEMORY READ,
MEMORY WRITE, INPUT, OUTPUT, FETCH, and INTERRUPT functions
from the processor (wherever it is) to assess board performance.
Bus emulators contain a basic I/O port, but include local memory behind the
port for caching digital test patterns as well, giving considerably more control over
speed and timing. Emulators offer three types of channels: address field, data field,
and timing or control channels. Logic levels are fixed, and the system controls timing