Page 29 - Building A Succesful Board-Test Strategy

What Is a Test Strategy? 15

the table would exhibit the problem. The resulting public-relations nightmare
forced Intel to provide a replacement for any such Pentium at no cost to the com-
puter customer—but an enormous expense for the company. The entire episode
vividly illustrated that although electronic systems had become vastly more
complex than they were only a few years ago, buyers of those systems have no
tolerance at all for known bugs.
(Despite the fact that I understood how small the error really was, I must
admit that I replaced the Pentium on my own computer. Like many engineers, 1
have a philosophical aversion to enduring a known bug when the solution is offered
gratis. On the other hand, I was not so naive as to believe that by doing so I had
necessarily eliminated the only possible bug in that device, merely the only one that
I knew about.)
At the board level, if devices start out good, the problem seems simpler. Yet,
densely populated boards with hundreds of tiny surface-mounted components on
both sides can exhibit problems that elude simulation steps to reveal them because
they represent that last 2 or 3 percent of uncovered faults. At any stage, a new
problem may emerge, which is why the process diagram in Figure 1-2 contains so
many feedback loops. In addition, suppose instead of multitudes of individual
components, the board contains highly integrated application-specific integrated
circuits (ASICs) or similar alternatives. In that case, someone has to construct a
test for the ASICs themselves, which in many respects resembles a functional board
test, so test development becomes a series of separate but interrelated steps.
Again, if fault simulation fails, the design process loops back to schematic
capture. Complex designs often require several iterations before passing all of these
early steps. Once past fault simulation, the product moves into layout,

1.4.2 Making the Product

The layout step creates a physical board description, including placement of
traces, solder pads, vias (through-holes), and components. A design-rule check ver-
ifies that the layout conforms to the company's testability and manufacturability
requirements for a reliable, high-quality product. Problems can include logic nodes
under ball-grid arrays (BGAs) and other components, prohibiting either bed-of-
nails fixturing of the loaded board or guided probing for functional-failure analy-
sis. Perhaps test pads are too small or node spacing is 25 mils (.025") when the
design specifies no less than 50, again to facilitate probing. Design rules may
demand that all through-hole components reside on one side of the board or that
the circuit's logic partitioning permit in-circuit cluster testing.
Whereas DFT analysis depends on the board's logic, a design-rule check
examines its physical implementation. (One industry expert once observed that the
term "design-rule checking" itself might be the greatest piece of marketing that
test engineers in the electronics industry have ever done. Design rules are con-
straints that facilitate manufacturing and testing, two activities that many design
engineers would rather leave to their manufacturing-engineering counterparts.