Page 24 - Building A Succesful Board-Test Strategy

What Is a Test Strategy? 11

In fact, test is an integral part of a product's life from its inception. Consider
the sample design-and-test process in Figure 1-2. It begins with computer-aided
research and development (CARD). A subset of computer-aided design and
computer-aided engineering, CARD determines the product's function and begins
to formulate its physical realization.
The output from CARD proceeds to schematic capture, producing logical
information for design verification and analysis. Next comes logic simulation,
which requires both a schematic (along with supporting data) and stimulus-and-
response vectors. Either human designers or computer-aided engineering (CAE)
equipment can generate the vectors. The logic-simulation step must verify that the
theoretical circuit will produce the correct output signals for any legitimate input.
The question remains, however, how many stimulus vectors are enough? The
only answer is that, unless the input-stimulus set includes every conceivable input
combination, it is possible that the verification process will miss a design flaw,
If logic simulation fails, designers must return to schematic capture to ensure
correct translation from design concept to schematic representation. If no errors
are evident from that step, another pass through CARD may become necessary.
If logic simulation passes, indicating that the theoretical circuit correctly
expresses the designers' intentions, the next step is a design-for-testability (DFT)
analysis. Notice that this analysis occurs long before a physical product is available
for examination. At this point, there is not even a board layout. Design-for-
testability attempts to confirm that if a logic fault exists, there is a place in the
circuit to detect it.
If DFT analysis fails, engineers must return to schematic capture. Although
logic simulation has shown the schematic to perform as designers intended, the
circuit's logical structure prevents manufacturing operations from discovering if a
particular copy of the circuit is good or bad.
This tight loop of DFT analysis, schematic capture, and logic simulation con-
tinues until the DFT analysis passes. The product then proceeds to a fault simula-
tion. The analysis has determined that testing is possible. Fault simulation must:
determine if it is practical. For example, consider the test sequence necessary to
verify on-board memory. The test must proceed from a known state. If there is no
reset function, however, initializing the circuit before beginning the test may be
difficult or time-consuming. The test may require cycling the memory until it
reaches some known state before the test itself can begin. Similarly, if the memory
array is very large, the test may take too long to warrant its use in high-volume
production.
Similarly, fault simulation must determine the minimum number of func-
tional test vectors required for confidence that the circuit works. Each fault may
be testable, but achieving an acceptable fault coverage in a reasonable time during
production may not be practical.
Like logic simulation, fault simulation requires a set of vector inputs and their
expected responses. At the same time, however, these two techniques are funda-
mentally different. Logic simulation attempts to verify that the design works,