Page 30 - Building A Succesful Board-Test Strategy

16 BUILDING A SUCCESSFUL BOARD-TEST STRATEGY

Calling them design rules makes them a bit more palatable.) Failure at this step
requires returning to layout, if not all the way to schematic capture.
Once the layout passes the design-rule check, the engineer must back-anno-
tate the circuit simulations to ensure that they accurately reflect any design changes
to this point and that the circuit still works. These two steps require data on the
manufacturing operation, such as paste-printer and chip-shooter accuracies.
The design then proceeds to initial bare-board fabrication and inspection.
Third-party suppliers usually manufacture the boards, but most companies (or
their contract manufacturers) perform their own inspection of these early boards
to guarantee that they conform to the final design. Even after production ramp-
up, some manufacturers inspect the bare boards themselves, rather than relying on
vendors to provide good products.
If the preceding steps have been done correctly, a hardware design-verifica-
tion step after adding components to these early bare boards should not reveal any
surprises. Manufacturers should also perform a functional test on the boards and
analyze any failures. Theoretically, the only faults uncovered at this stage result
from the assembly process. Once design and manufacturing engineers are confident
that the board functions as intended and that the manufacturing process will
produce good boards, full production ramp-up can begin.
Notice the number of test activities that occur even before the first production-
type test after bare-board fabrication. Test never really was an isolated activity.

1.4.3 New Challenges

Today's components present greater challenges than ever before. As the gap
between a digital device's logic "0" and logic "1" continues to narrow, manufac-
turers must reduce noise at both the device and the board level. Therefore, new
designs tolerate much less noise than older ones did.
For example, with Gunning Transceiver Logic (GTL) and GTL+ (found in
many Pentium-class devices), open-drain signals require termination to a V TT
supply that provides the high signal level. Receivers use a threshold voltage (V REF)
to distinguish between a "1" and a "0". Unlike prior-generation PC systems, these
designs include a tolerance requirement for V TT of 1.5 V ± 3% while the system bus
is idle. A reliable system requires proper design techniques and a consistent, reli-
able termination. In this case, termination resistors must be 56O ± 5%.
Ever-lower noise margins also increase the circuit's vulnerability to "ground
bounce." As speeds increase, transient-switching currents increase as well, creating
a brief ground-level bounce as the current flows through the inductance of the
ground pins. Through modeling, designers can predict this phenomenon. Never-
theless, you should permit no open ground pins during manufacturing.
Another issue complicating test-strategy decisions relates to the much stricter
standards on EMI that international regulators have imposed on electronics
manufacturers. In the U.S., the Federal Communications Commission demands no
EMI between consumer products. Companies selling to customers in Europe must
comply with even stricter requirements, as the European Community tries to ensure