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4.3 / ELEMENTS OF CACHE DESIGN 135

1.0
0.9
0.8
0.7
Hit ratio 0.6
0.5
0.4
0.3
0.2
0.1
0.0
1k 2k 4k 8k 16k 32k 64k 128k 256k 512k 1M
Cache size (bytes)
Direct
2-way
4-way
8-way
16-way
Figure 4.16 Varying Associativity over Cache Size

It significantly improves the hit ratio over direct mapping. Four-way set associative
(n = m/4, k = 4 ) makes a modest additional improvement for a relatively small ad-
ditional cost [MAYB84, HILL89]. Further increases in the number of lines per set
have little effect.
Figure 4.16 shows the results of one simulation study of set-associative cache
performance as a function of cache size [GENU04]. The difference in performance
between direct and two-way set associative is significant up to at least a cache size of
64 kB. Note also that the difference between two-way and four-way at 4 kB is much
less than the difference in going from for 4 kB to 8 kB in cache size.The complexity
of the cache increases in proportion to the associativity, and in this case would not
be justifiable against increasing cache size to 8 or even 16 Kbytes. A final point to
note is that beyond about 32 kB, increase in cache size brings no significant increase
in performance.
The results of Figure 4.16 are based on simulating the execution of a GCC
compiler. Different applications may yield different results. For example, [CANT01]
reports on the results for cache performance using many of the CPU2000 SPEC
benchmarks.The results of [CANT01] in comparing hit ratio to cache size follow the
same pattern as Figure 4.16, but the specific values are somewhat different.

Cache Simulator
Multitask Cache Simulator