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4.3 / ELEMENTS OF CACHE DESIGN 139

DRAM or ROM memory across the bus.Due to the typically slow bus speed and slow
memory access time, this results in poor performance. On the other hand, if an L2
SRAM (static RAM) cache is used, then frequently the missing information can be
quickly retrieved. If the SRAM is fast enough to match the bus speed, then the data
can be accessed using a zero-wait state transaction, the fastest type of bus transfer.
Two features of contemporary cache design for multilevel caches are noteworthy.
First, for an off-chip L2 cache, many designs do not use the system bus as the path
for transfer between the L2 cache and the processor, but use a separate data path, so
as to reduce the burden on the system bus. Second, with the continued shrinkage of
processor components, a number of processors now incorporate the L2 cache on the
processor chip, improving performance.
The potential savings due to the use of an L2 cache depends on the hit rates in
both the L1 and L2 caches. Several studies have shown that, in general, the use of
a second-level cache does improve performance (e.g., see [AZIM92], [NOVI93],
[HAND98]). However, the use of multilevel caches does complicate all of the design
issues related to caches, including size, replacement algorithm, and write policy; see
[HAND98] and [PEIR99] for discussions.
Figure 4.17 shows the results of one simulation study of two-level cache per-
formance as a function of cache size [GENU04]. The figure assumes that both
caches have the same line size and shows the total hit ratio.That is, a hit is counted if
the desired data appears in either the L1 or the L2 cache. The figure shows the im-
pact of L2 on total hits with respect to L1 size. L2 has little effect on the total num-
ber of cache hits until it is at least double the L1 cache size. Note that the steepest
part of the slope for an L1 cache of 8 Kbytes is for an L2 cache of 16 Kbytes. Again
for an L1 cache of 16 Kbytes, the steepest part of the curve is for an L2 cache size of
32 Kbytes. Prior to that point, the L2 cache has little, if any, impact on total cache

0.98

0.96
0.94
0.92
0.90 L1 16k
Hit ratio 0.88 L1 8k

0.86
0.84
0.82

0.80
0.78
1k 2k 4k 8k 16k 32k 64k 128k 256k 512k 1M 2M
L2 cache size (bytes)
Figure 4.17 Total Hit Ratio (L1 and L2) for 8-Kbyte and 16-Kbyte L1