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System bus L3 cache (1 MB) L2 cache (512 KB)
256 bits
64 bits
Instruction fetch/decode unit FP register file FP move unit
FP/ MMX unit
L1 instruction cache (12K ops) Complex integer ALU
Simple integer ALU L1 data cache (16 KB)
Out-of-order execution logic Integer register file Simple integer ALU
Store address unit Pentium 4 Block Diagram
Load address unit Figure 4.18
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